A conventional use of D-Type Flip-Flops is in the provision of frequency dividers. The flip-flop is used in the configuration shown in FIG. 1a of the accompanying drawings. As shown, a D-type flip flop 10 has a clock input CK, an input D and outputs Q and Q. If the Q output is fed to the input D, then a signal of frequency F.sub.o e.g. a clock signal, fed to the clock input CK provides an output at the Q output of a signal of frequency F.sub.o /2.
To prevent "feed-through", such flip-flops are usually of the "master/slave" type, the "master" being clocked on, for example, a first edge of an input pulse of the input signal, and the "slave" being clocked on a second edge of the input pulse of the input signal.
A single input signal CK may be fed to the input of the master section of the master/slave flip-flop and, through an invertor, to the input of the slave section of the flip-flop. Alternatively, CK and CK signals may be fed respectively to clock the master and slave sections of the flip-flop.
FIG. 1b of the accompanying drawings illustrates a known master/slave D-type flip-flop.
In FIG. 1b, it will be seen that a master section A is substantially identical to a slave section B. Like points in the slave section are given the same reference numeral as in the master section but with a prime. Each section comprises a tracking part and a latching part. External connections are available at D, D, Q and Q and enternal (equivalent) points are indicated at at D', D, Q' and Q'. Clock input terminals CK and CK are also shown and serve to clock respectively, the latch part of master section A and the tracking part of slave section B, and the tracking part of master section A and the latch part of slave section B. Each track part comprises a pair of transistors 12 the ON or OFF state of which is determined firstly by a transistor 14 connecting their emitters to ground via a current sink I.sub.r and secondly by the potential appearing on their bases D and D. The transistor 14 is switched on by the clock signal CK and the transistor 14' is switched on by the clock signal CK. The two tracking parts thus work in opposite phase. The collectors of transistors 12 are connected to a voltage rail 16 and to the bases D' and D' of the transistors 12'.
Each latch part comprises a pair of transistors 18 having their emitters connected through a transistor switch 20 to the current sink I.sub.r. The transistor switch 20 is closed by the application of a pulse to the CK input; the switch 20' being closed by the application of a pulse to the CK input.
The bases of a first transistor of the pair 18 is connected to the bases of a second transistor of the pair 12'.
The base of a second transistor of the pair 18 is connected to voltage rail 16 and to the collector of a first transistor of the pair 12.
The base of a first transistor of the pair 18' is connected to voltage rail 16 and to the base of a first transistor of the pair 12. The base of a second transistor of the pair 18' is connected to voltage rail 16 and to the base of the second transistor of the pair 12.
In operation, on receipt of a clock pulse CK, one or the other of the transistor pair 18 will conduct, due initially to imbalance of the circuit, and whatever voltage appears on the collector Q' of the transistor pair 18 (the latch part of the master section) will be tracked by the tracking part of the slave section to base D' of the transistor pair 12'.
On the application of an input to the CK input, the first transistor of the pair 12', if it conducts, will provide a "0" output at the Q output of the flip-flop, that is at the collector of the second transistor. Simultaneously, whatever value was present on the collector of the first transistor of the pair 18' in the latch part of the slave section, that is the Q output is tracked to the base, the D input, of the second transistor of the transistor pair 12 of the track part of the master section of the flip-flop.
If a signal of frequency F.sub.o is applied to the CK input, and, in antiphase, to the CK input, a signal of frequency F.sub.o.sup./2 can be taken from the Q output of the flip-flop. Internally of the flip-flop, an input (CK or CK) is acted on by the track part of one section and the latch part of the other section and transferred, on the next input, to the latch part of the same section and the track part of the other section. In this way, there is no feed through and the resultant output is at half the frequency of the input signal. Two D-type flip-flops connected in series give a divide by four frequency divider and so on.
Whilst it is essential to avoid feedthrough, the tracking and latching parts of each section of the master/slave flip-flop double the number of parts necessary merely to provide the divide by 2 function.
It is an object of the present invention to provide an improved master/slave flip-flop for high frequency operation, wherein, whilst feed through is prevented, separate tracking and latching parts are not necessary.